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1 of 64 proprietary & confidential GS6150 final data sheet rev.2 pds-060127 march 2015 gennum products GS6150 GS6150 multi-rate 6g uhd-sdi reclocker www.semtech.com key features ? smpte st 2081, st 424, st 292, and st 259-c compliant ? supports retiming data at rates of 125mb/s, 270mb/s, 1.485 and 1.485/1.001gb/s, 2.97 and 2.97/1.001gb/s, 5.94 and 5.94/1.001gb/s ? supports retiming of dvb-asi signals ? automatic or manual rate selection ? detected rate indication in auto mode ? 4:1 input selector patented technology ? option of two reclocked data outputs ? four configurable gpio pins with ability to output device status, including: ? lock detect ? loss of signal (los) ? low/high bit-rate indication for slew-rate control of sdi cable drivers ? on-chip 100 differential input and output termination ? bypass support for rates up to 5940mb/s ? manual bypass function ? configurable automatic bypass when not locked ? option to use external reference or operate referenceless ? cascading reference buffer supports multiple reclockers using a single reference source ? input signal equalization and output signal de-emphasis to compensate for trace dielectric losses ? single power supply operation at 1.8v ? 130mw typical power consumption (150mw with second output enabled) ? pb-free and rohs compliant ? operating temperature range: -40c to 85c applications ? smpte st 2081, smpte st 424, smpte st 292, smpte st 259-c coaxial cable serial digital interfaces ? en50083-9 dvb-asi interfaces ? madi standard description the GS6150 is a low-power, multi-rate serial digital reclocker designed to automatically recover the embedded clock from a digital video sign al and re-time the incoming video data. the GS6150 will recover the embedded clock signal and re- time the data from 6g uhd- sdi signals compliant with smpte st 2081. in addition, it can also re-time smpte st 259-c, smpte st 292, smpte st 424 or dvb-asi compliant digital video signals as well as madi audio streams. the GS6150 features four high -speed differential signal inputs feeding a 4:1 input sele ctor. input termination is on- chip for seamless matching to 100 differential transmission lines. the input selector is a component of a video switching system with tightly constrained timing requirements. the GS6150 includes programmable trace equalization to compensate for high-frequen cy losses associated with board-level interconnect. two cml outputs interface seamlessly to devices with a cml input reference between 1.2v and 2.5v. programmable output swing and de-emphasis provide flexibility in managing signal in tegrity of the output signals. the GS6150 can operate in eith er automatic rate detection or manual rate selection mode . in auto mode the device will automatically detect and lock onto incoming data signals at any supported rate.
GS6150 final data sheet rev.2 pds-060127 march 2015 2 of 64 proprietary & confidential www.semtech.com the device can operate without an external 27mhz frequency reference. for appl ications which require rapid signal lock, an external 27mhz reference may be used to set the vco frequency when not lock ed to the input signal. the presence of an external reference crystal is automatically detected by the device. in systems that re quire passing of non-supported data rates, the GS6150 ca n be configured to either automatically or manually enter a bypass mode in order to pass the signal without reclocking. a four-wire serial gennum serial peripheral interface (gspi) facilitates configuration and status monitoring of the device. multiple GS6150 devic es can be daisy-chained together with a single 4-pin co nnection to the host system. this device is pb-free, an d the encapsulation compound does not contain halogenated flame retardant. this component and all homoge nous sub-components are rohs compliant. GS6150 functional block diagram gpio0 ddi_sel[1:0]/ strobe ddi3 ddi2 ddi1 ddi0 xtal_clk_in xtal_clk_out xtal_buf_out xtal oscillator buffer phase frequency detector phase detector reference divide los detect control selectable divide charge pump vco retimer equalizer/ data mux spi sdin sclk sdo ddo0 ddo1 data buffer lf+, lfC oscillator ddo1 ddo0 ddi0 ddi1 ddi2 ddi3 gpio1 gpio2 gpio3 data buffer cs
GS6150 final data sheet rev.2 pds-060127 march 2015 3 of 64 proprietary & confidential www.semtech.com revision history contents 1. pin out..................................................................................................................... ............................................5 1.1 pin assignment ............................................................................................................ .......................5 1.2 pin descriptions .......................................................................................................... ........................6 2. electrical characteristics.................................................................................................. ........................... 10 2.1 absolute maximum ratings .................................................................................................. ...... 10 2.2 dc electrical characteristics ............................................................................................. ........... 10 2.3 ac electrical characteristics ............................................................................................. ............ 12 3. input/output circuits....................................................................................................... ........................... 15 4. detailed description........................................................................................................ ............................ 17 4.1 serial data inputs ........................................................................................................ ..................... 17 4.1.1 input trace equalization ................................................................................................. .. 17 4.1.2 input selection .......................................................................................................... ........... 17 4.2 reference clock ........................................................................................................... ..................... 19 4.3 signal monitoring ......................................................................................................... ................... 19 4.3.1 loss of signal detection................................................................................................. ... 19 4.3.2 lock detection .......................................................................................................... .......... 21 4.3.3 rate detection........................................................................................................... ........... 22 4.3.4 low/high bit rate detection for slew rate control ............................................... 23 4.4 low power modes ........................................................................................................... ................ 23 4.5 serial data output ........................................................................................................ ................... 24 4.5.1 output impedance ......................................................................................................... .... 24 4.5.2 output signal interface levels ....................................................................................... 24 4.5.3 adjustable output swing................................................................................................. 2 4 4.5.4 output de-emphasis....................................................................................................... ... 25 4.5.5 output common mode voltage.................................................................................... 26 4.6 output mute, disable, and data selection ............................................................................. 26 4.7 bypass mode ............................................................................................................... ...................... 27 4.8 dvb-asi ................................................................................................................... ............................ 27 version eco pcn date changes and/or modifications 2 024967 march 2015 updated table 2-2 and table 2-3 . updated section 4.11 and section 5. updated to final data sheet. 1 022115 september 2014 changed product title. updated table 5-1 format. updates throughout table 2-2 and table 2-3 . added section 4.5.5 . updated table 5-1 . 0 016784 december 2013 new document
GS6150 final data sheet rev.2 pds-060127 march 2015 4 of 64 proprietary & confidential www.semtech.com 4.9 device power up ........................................................................................................... .................. 27 4.9.1 power on reset (por) ..................................................................................................... ... 27 4.9.2 reset pin (rst) .......................................................................................................... ............ 27 4.10 gpio pins configuration .................................................................................................. ........... 27 4.11 gspi host interface ...................................................................................................... ................. 29 4.11.1 cs pin........................................................................................................................... .......... 29 4.11.2 sdin pin................................................................................................................ ................ 29 4.11.3 sdout pin ............................................................................................................... ............ 29 4.11.4 sclk pin................................................................................................................ ................ 31 4.11.5 command word description........................................................................................ 31 4.11.6 gspi transaction timing ................................................................................................ 3 4 4.11.7 single read/write access............................................................................................... 3 6 4.11.8 auto-increment read/write access ........................................................................... 37 4.11.9 setting a device unit address...................................................................................... 38 4.11.10 default gspi operation ................................................................................................ 3 9 5. host interface register map................................................................................................. ..................... 41 6. typical application circuit ................................................................................................. ....................... 60 7. package and ordering information ............................................................................................ ........... 61 7.1 package dimensions ........................................................................................................ .............. 61 7.2 recommended pcb footprint ................................................................................................. ... 62 7.3 packaging data ............................................................................................................ .................... 62 7.4 marking diagram ........................................................................................................... .................. 63 7.5 solder reflow profile ..................................................................................................... ................. 63 7.6 ordering information ...................................................................................................... ............... 63
GS6150 final data sheet rev.2 pds-060127 march 2015 5 of 64 proprietary & confidential www.semtech.com 1. pin out 1.1 pin assignment figure 1-1: GS6150 pin out ddi0 gnd ddi1 ddi2 ddi3 gnd gnd gpio0 ddo0 vcc_ddo0 vee_ddo vee_ddo vcc_ddo1 ddo1 gpio3 gpio1 ddi_sel0/strobe ddi_sel1 xtal_clk_in xtal_clk_out xtal_buf_out sdin sdout sclk vdd_dig vss_dig vee_core vcc_core vco_filt lf? lf+ vee_core vcc_core rsv_41 rsv_39 rsv_38 rsv_37 GS6150 48-pin qfn (6x6mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 ddi0 ddi1 ddi2 ddi3 cs gpio2 rst ddo1 ddo0 rsv_40 vee_ddo
GS6150 final data sheet rev.2 pds-060127 march 2015 6 of 64 proprietary & confidential www.semtech.com 1.2 pin descriptions table 1-1: GS6150 pin descriptions pin number name type description 1, 2 ddi0, ddi0 input serial digital differential input 0. 3, 6, 9 gnd power input channel isolation. connect to ground or leave unconnected. 4, 5 ddi1, ddi1 input serial digital differential input 1. 7, 8 ddi2, ddi2 input serial digital differential input 2. 10, 11 ddi3, ddi3 input serial digital differential input 3. 12 gpio0 digital input/output multi-function control/status input/output 0. signal options are: los (output; default) locked lbr_hbr rate_det0 rate_det1 rate_det2 locked_125m locked_270m locked_1g485 locked_2g97 locked_5g94 rate_change ddo0_disable ddo1_disable this pin is configured using the gpio0_select and gpio0_io_select bits in the gpio_control_reg_0 register. 13 gpio1 digital input/output multi-function control/status input/output 1. signal options are: los locked (output; default) lbr_hbr rate_det0 rate_det1 rate_det2 locked_125m locked_270m locked_1g485 locked_2g97 locked_5g94 rate_change ddo0_disable ddo1_disable this pin is configured using the gpio1_select and gpio1_io_select bits in the gpio_control_reg_0 register.
GS6150 final data sheet rev.2 pds-060127 march 2015 7 of 64 proprietary & confidential www.semtech.com 14, 15 ddi_sel0/strobe, ddi_sel1 logic input input selection control. used to select the high-speed input for processing through the device. refer to table 4-1 for details on input selection. 16 xtal_clk_in input reference crystal pin/27mhz clock input. connect to an external circuit as shown in figure 6-1: GS6150 typical application circuit or to a digital clock source (xtal_buf_out of another GS6150 or gs6151). connect to ground if operating referenceless. 17 xtal_clk_out output reference crystal pin. connect to a external circuit as shown in figure 6-1: GS6150 typical application circuit , or leave unconnected if xtal_clk_in is driven by an external clock source or if xtal_clk_in is connected to ground (referenceless). 18 xtal_buf_out output buffered clock reference output. le ave unconnected if not used to drive 27mhz clock input of another device. 19 sdin digital input serial digital data input for the gennum serial peripheral interface (gspi) host control/status port. refer to 4.11 gspi host interface for more details. 20 sdout digital output serial digital data output for the gennum serial peripheral interface (gspi) host control/status port. refer to 4.11 gspi host interface for more details. 21 sclk digital input burst-mode clock input for the gennum serial peripheral interface (gspi) host control/status port. refer to 4.11 gspi host interface for more details. 22 cs digital input chip select input for the gennum serial peripheral interface (gspi) host control/status port. active-low input. refer to 4.11 gspi host interface for more details. 23 vdd_dig power most positive power supply for the internal logic connect to 1.8v. 24 vss_dig power most negative power supply for the internal logic connect to ground. table 1-1: GS6150 pin descri ptions (continued) pin number name type description
GS6150 final data sheet rev.2 pds-060127 march 2015 8 of 64 proprietary & confidential www.semtech.com 25 gpio2 digital input/output multi-function control/status input/output 2. signal options are: los locked lbr_hbr (output; default) rate_det0 rate_det1 rate_det2 locked_125m locked_270m locked_1g485 locked_2g97 locked_5g94 rate_change ddo0_disable ddo1_disable this pin is configured using the gpio2_select and gpio2_io_select bits in the gpio_control_reg_1 register. 26 gpio3 digital input/output multi-function control/status input/output 3. signal options are: los locked lbr_hbr rate_det0 rate_det1 rate_det2 locked_125m locked_270m locked_1g485 locked_2g97 locked_5g94 rate_change ddo0_disable ddo1_disable (input; default) this pin is configured using the gpio3_select and gpio3_io_select bits in the gpio_control_reg_1 register. 27 rst digital input reset pin. if set low, all blocks set to default conditions and inputs/ outputs set to high impedance. if high, normal operation of the device resumes. by default, internally pulled high. 28 vcc_ddo1 power most positive power supply connection for the ddo1/ddo1 output driver. connect to any voltage between 1.2v and 2.5v. 29, 32, 35 vee_ddo power most negative power supply connections for the output drivers. connect to ground. 30, 31 ddo1 , ddo1 output differential serial data output 1. 33, 34 ddo0 , ddo0 output differential serial data output 0. 36 vcc_ddo0 power most positive power supply connection for the ddo0/ddo0 output driver. connect to any voltage between 1.2v and 2.5v. table 1-1: GS6150 pin descri ptions (continued) pin number name type description
GS6150 final data sheet rev.2 pds-060127 march 2015 9 of 64 proprietary & confidential www.semtech.com 37 rsv_37 power decoupling connect through decoupling capacitor to ground. 38 rsv_38 power connect to 1.8v. 39 rsv_39 power connect to ground. 40, 41 rsv_40, rsv_41 input leave unconnected. 42 vcc_core power most positive power supply connection to the analog core connect to 1.8v. 43 vee_core power most negative power supply connection to the analog core connect to ground. 44 lf+ passive connect to lfC through c lf refer to figure 6-1: GS6150 typical application circuit . 45 lfC passive connect to lf+ through c lf refer to figure 6-1: GS6150 typical application circuit . 46 vco_filt power external decoupling for the vco. refer to figure 6-1: GS6150 typical application circuit . 47 vcc_core power most positive power supply connection for the analog core connect to 1.8v. 48 vee_core power most negative power supply connection to the analog core connect to ground. center pad power ground pad on bottom of package. table 1-1: GS6150 pin descri ptions (continued) pin number name type description
GS6150 final data sheet rev.2 pds-060127 march 2015 10 of 64 proprietary & confidential www.semtech.com 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics table 2-1: absolute maximum ratings parameter value supply voltage C core (vcc_core, vdd_dig) C0.5 to +2.1v dc supply voltage C output driver (vcc_ddo0, vcc_ddo1) C0.5 to +2.8v dc input esd voltage 4kv storage temperature range (t s ) C50oc to +125oc operating temperature range (t a ) C40oc to +85oc input voltage range (any input pin) C0.3 to (v cc_core + 0.3)v dc solder reflow temperature +260oc note: absolute maximum ratings are those va lues beyond which damage may occur. functional operation outside of the ranges shown in the ac/dc electrical characteristics tables is not guaranteed. table 2-2: dc electrical characteristics vcc_core, vdd_dig = +1.8v 5%, t a = C40oc to +85oc unless otherwise specified parameter symbol conditions min typ max units notes supply voltage C core (vcc_core, vdd_dig) v cc_core , v dd_dig 1.710 1.8 1.890 v supply voltage C output driver (vcc_ddo0, vcc_ddo1) v cc_ddo0 , v cc_ddo1 1.140 2.625 v
GS6150 final data sheet rev.2 pds-060127 march 2015 11 of 64 proprietary & confidential www.semtech.com power p d data rate 6g, ddo1/ddo1 disabled 140 185 mw 1 , 2 data rate <6g, ddo1/ddo1 disabled 130 170 mw 1 , 2 data rate 6g, default settings, ddo1/ddo1 enabled 210 280 mw 3 , 4 data rate <6g, default settings, ddo1/ddo1 enabled 190 255 mw 3 , 4 maximum supply and power settings 280 360 mw 5 power (sleep operation) p sleep 20 35 mw power (standby operation) p standby 80 110 mw supply current - output driver i cc_ddo0 , i cc_ddo1 output swing register setting = 0000 b 4.8 7ma 6 , 7 output swing register setting= 0100 b 7.512ma 6 , 7 output swing register setting = 1100 b 1522ma 6 , 7 supply current - core i cc_core output de-emphasis disabled data rate 6g 82ma 8 output de-emphasis disabled data rate 3g 74ma 8 output de-emphasis enabled data rate 6g 90ma 8 output de-emphasis enabled data rate 3g 81ma 8 supply current - digital i cc_dig external crystal referenced 7 12 ma serial input termination differential 75 100 125 serial output termination differential 75 100 125 serial input common mode voltage v cmin 0.9 v cc_core - 50mv v 9 , 10 table 2-2: dc electrical characteristics (continued) vcc_core, vdd_dig = +1.8v 5%, t a = C40oc to +85oc unless otherwise specified parameter symbol conditions min typ max units notes
GS6150 final data sheet rev.2 pds-060127 march 2015 12 of 64 proprietary & confidential www.semtech.com 2.3 ac electrical characteristics input voltage - digital pins (cs , sdin, clk, gpio[0:3]) v ih 0.65* vdd_dig vdd_dig v v il 0 0.35* vdd_dig v output voltage - digital pins (sdout, gpio[0:3]) v oh i oh = -2ma vdd_dig C 0.45 v v ol i ol = 2ma 0.45v notes: 1. normal operation in referenceless mode, mi nimum output swing with de-emphasis disabled 2. vcc_ddo0/1 = 1.2v 3. the swing is default and de-emphasis is on 4. vcc_ddo0/1 = 1.8v 5. ddo0/ddo0 and ddo1/ddo1 set to maximum swing setting, external crystal reference used 6. consumption per enabled ddo output 7. refer to table 4-3 for the exact register settings for each v ddo output swing listed 8. for two enabled outputs 9. maximum input voltage level = 1.8v 5% 10. up to a maximum swing of 800mv table 2-2: dc electrical characteristics (continued) vcc_core, vdd_dig = +1.8v 5%, t a = C40oc to +85oc unless otherwise specified parameter symbol conditions min typ max units notes table 2-3: ac electrical characteristics vcc_core, vdd_dig = +1.8v 5%, t a = C40oc to +85oc unless otherwise specified parameter symbol conditions min typ max units notes input data rate (bypass) dr bypass bypass mode enabled 3 5940 mb/s 1 input sensitivity v sdi differential 200 800 mv ppd output voltage swing v ddo output swing register setting = 0100 b 310 410 510 mv ppd 2 output swing register setting = 1100 b 600 800 1000 mv ppd 2 serial input jitter tolerance ijt square wave modulation 0.8 ui pll lock time asynchronous t alock referenceless 50 ms with external reference (madi enabled) 30ms with external reference (madi disabled) 20ms
GS6150 final data sheet rev.2 pds-060127 march 2015 13 of 64 proprietary & confidential www.semtech.com pll lock time synchronous t slock referenceless 10 s with external reference 10 s serial data (ddo0 and ddo1) output rise and fall time t riseddo 20% ~ 80% rising edge into 50 load 70ps t fallddo 20% ~ 80% falling edge into 50 load 70ps rise and fall time mismatch (ddo0 and ddo1) 15ps duty cycle distortion (ddo0 and ddo1) data rate 6g 10 % data rate < 6g 5 % serial data output jitter intrinsic t oj(125mb/s) bw = nominal prn 2 23 C 1 test pattern 0.02 0.03 ui p-p 3 , 4 t oj(270mb/s) 0.02 0.03 ui p-p 3 , 4 t oj(1485mb/s) 0.03 0.06 ui p-p 3 , 4 t oj(2970mb/s) 0.04 0.09 ui p-p 3 , 4 t oj(5940mb/s) 0.07 0.13 ui p-p 3 , 4 t oj(bypass) 0.06 0.09 ui p-p 3 , 4 pll loop bandwidth bw loop(125mb/s) pll_loop_bandwidth = 00001 37khz pll_loop_bandwidth = 00010 74khz pll_loop_bandwidth = 00100 (default) 148 khz pll_loop_bandwidth = 01000 296 khz pll_loop_bandwidth = 10000 590 khz bw loop(270mb/s) pll_loop_bandwidth = 00001 80khz pll_loop_bandwidth = 00010 160 khz pll_loop_bandwidth = 00100 (default) 320 khz pll_loop_bandwidth = 01000 640 khz pll_loop_bandwidth = 10000 1.28mhz table 2-3: ac electrical characteristics (continued) vcc_core, vdd_dig = +1.8v 5%, t a = C40oc to +85oc unless otherwise specified parameter symbol conditions min typ max units notes
GS6150 final data sheet rev.2 pds-060127 march 2015 14 of 64 proprietary & confidential www.semtech.com pll loop bandwidth bw loop(1485mb/s) pll_loop_bandwidth = 00001 438 khz pll_loop_bandwidth = 00010 875 khz pll_loop_bandwidth = 00100 (default) 1.75mhz pll_loop_bandwidth = 01000 3.5mhz pll_loop_bandwidth = 10000 7mhz bw loop(2970mb/s) pll_loop_bandwidth = 00001 875 khz pll_loop_bandwidth = 00010 1.75mhz pll_loop_bandwidth = 00100 (default) 3.5mhz pll_loop_bandwidth = 01000 7.0mhz pll_loop_bandwidth = 10000 14.0 mhz bw loop(5940mb/s) pll_loop_bandwidth = 00001 1.75mhz pll_loop_bandwidth = 00010 3.5mhz pll_loop_bandwidth = 00100 (default) 7.0mhz pll_loop_bandwidth = 01000 14.0 mhz pll_loop_bandwidth = 10000 28.0 mhz note: 1. edge detection method for los detection sh ould be used for data rates below 20mb/s 2. refer to table 4-3 for the exact register settings for each v ddo output swing listed 3. jitter measured using an oscilloscope according to smpte rp-184 4. accumulated jitter measured peak to peak differential over 2000 hits table 2-3: ac electrical characteristics (continued) vcc_core, vdd_dig = +1.8v 5%, t a = C40oc to +85oc unless otherwise specified parameter symbol conditions min typ max units notes
GS6150 final data sheet rev.2 pds-060127 march 2015 15 of 64 proprietary & confidential www.semtech.com 3. input/output circuits figure 3-1: ddi0, ddi0 , ddi1, ddi1 , ddi2, ddi2 , ddi3, ddi3 serial digital di fferential inputs figure 3-2: ddo0, ddo0 , ddo1, ddo1 serial digital differential output figure 3-3: sdin and sclk figure 3-4: sdout figure 3-5: cs figure 3-6: rst 50 50 ddi ddi vcc_core vcc_core vcc_core rlc rlc 18.5k 3.7k 50 50 ddo ddo vcc_ddo0/1 vcc_ddo0/1 vcc_ddo0/1 100k vdd_dig vdd_dig sdin, sclk sdout vdd_dig vdd_dig 100k vdd_dig vdd_dig vdd_dig cs rst vdd_dig vdd_dig vdd_dig
GS6150 final data sheet rev.2 pds-060127 march 2015 16 of 64 proprietary & confidential www.semtech.com figure 3-7: ddi_sel0/ strobe and ddi_sel1 figure 3-8: xtal_buf_out figure 3-9: general purpos e inputs/outputs (gpio) figure 3-10: xtal_clk_in and xtal_clk_out 100k vdd_dig vdd_dig ddi_sel0, ddi_sel1 vdd_dig vdd_dig xtal_buf_out vdd_dig gpio 100k 1k note: gpio interface includes pins gpio0, gpio1, gpio2, and gpio3 vdd_dig vdd_dig vdd_dig vdd_dig xtal_clk_out en vdd_dig en vdd_dig 246 246 vdd_dig xtal_clk_in
GS6150 final data sheet rev.2 pds-060127 march 2015 17 of 64 proprietary & confidential www.semtech.com 4. detailed description the GS6150 is a multi-standard reclocker for serial digital sdtv sdi and dvb-asi signals operating at 270mb/s, hdtv sdi signals operating at 1.485gb/s and 1.485/1.001gb/s, 3g sdi signals operating at 2.97gb/s and 2.97/1.001gb/s, and 6g uhd-sdi signals operating at 5.94gb/s and 5.94/1.001gb /s and madi audio streams at 125mb/s. 4.1 serial data inputs the GS6150 features four 100 terminated differential input buffers. a serial data input signal may be connected to any of the following input pin pairs of the device: ddi0/ddi0 , ddi1/ddi1 , ddi2/ddi2 , and ddi3/ddi3. by default, the self-biasing circuit at the input is enabled to allow ac coupling to upstream devices. to enable dc coupling of the inputs, the user must disable the self- biasing network by setting bits 4:4 through 5:5 to 0 in the register 7 h : ddi[0:1]_trace_eq_dc_term_enable. in order to select dc coupling, please ensure that the output common mode of the upstream device is in range of the in put common mode voltage range shown in table 2-2 . the serial digital input buffer is capable of operation with any binary coded signal that meets the input signal level requirements de fined below, with an y data rate between 3mb/s and 5.94gb/s. 4.1.1 input trace equalization the GS6150 features adjustable trace eq ualization to compe nsate for pcb trace dielectric losses up to half the maximum supported data rate , or 3ghz. the equalization has three settings: the low (default) setting is optimized for compensating the high- frequency losses associated with 0-7db of trace loss at 1.5ghz for data rates of 2.97gb/s and below, and for 0-10db of trace loss at 3ghz for 5.94gb/s. the high setting is optimized for trace loss between 7-14db at 1.5ghz for data rates 2.97gb/s and below. the 0db or eq_bypass setting may be used in systems with negligib le trace loss. these settings are selected using the ddi0_trace_eq_control, ddi1_trace_eq_control, ddi2_trace_eq_control and ddi3_trace_eq_control bits in the input_control_reg_ 0 register at address 5 h . the default state of the device is input trac e equalization on all inputs set to low. 4.1.2 input selection the GS6150 incorporates a 4:1 input selector which allows the connection of four independent streams of video/data. the selector is controllable in three separate ways:
GS6150 final data sheet rev.2 pds-060127 march 2015 18 of 64 proprietary & confidential www.semtech.com 1. the ddi_sel0 and ddi_sel1 pins can be used to select the input. 2. a gspi accessible register can be used to select the input, with the state change occurring as soon as th e register value changes. 3. a gspi accessible register can be used to select the input, with a rising edge on the strobe pin triggering a change to the next state. since these states are mutually exclusive, th e ddi_sel0 pin is shared with the strobe function. in the case of using the ddi_sel0/strobe and ddi_sel1 pins (#1 above) or the strobe pre-select method (#3 above), the input selector will switch within 1s of the change of state on the corresponding pin(s). this strict timing requirement is not maintained when using gspi register selection (#2 above). each of the devices four inpu ts is selected as shown in table 4-1 . the ddi_sel0/strobe and ddi_sel1 pins incl ude internal pull-downs, which pulls the input voltage low if eith er pin is unconnected. when using the strobe pre-select method (#3 above), the pre-selected input buffer and trace eq is powered up in advance of the strobe pulse. table 4-1: pin and register se ttings for input selection register settings pin settings differential high-speed input selected input_selection_control 7 h [9:8] ddi_select 7 h [11] ddi_select 7 h [10] ddi_sel1 ddi_sel0/ strobe x0 (default) x x low low ddi0, ddi0 x0 (default) x x low high ddi1, ddi1 x0 (default) x x high low ddi2, ddi2 x0 (default) x x high high ddi3, ddi3 01 0 0 x x ddi0, ddi0 01 0 1 x x ddi1, ddi1 01 1 0 x x ddi2, ddi2 01 1 1 x x ddi3, ddi3 11 0 0 x on low-to- high transition ddi0, ddi0 11 0 1 x on low-to- high transition ddi1, ddi1 11 1 0 x on low-to- high transition ddi2, ddi2 11 1 1 x on low-to- high transition ddi3, ddi3 note: x indicates do not care
GS6150 final data sheet rev.2 pds-060127 march 2015 19 of 64 proprietary & confidential www.semtech.com 4.2 reference clock the GS6150 can operate with or without an external frequency reference. for applications requiring rapid asynchronous locking, a 27mhz reference or crystal is required. the pll lock times for both referenceless and external crystal reference operation are given in table 2-3: ac electrical characteristics . if a reference is connected to the xtal_clk_in pin or a crystal is connected to the xtal_clk_in and xtal_clk_out pins of the devic e, it will automatically be used as the reference frequency for rapid asynchronous lock. if xtal_c lk_in is not connected to a crystal, xtal_clk_out mu st be left unconnected. the xtal_clk_in pin operates correctly when connected directly to the xtal_buf_out from another GS6150, or a 27mhz output of a different device. 4.3 signal monitoring the GS6150 measures and reports the following signal status and quality monitoring parameters: ? loss of signal ? lock detection ? rate detection ? low/high bit rate detection 4.3.1 loss of signal detection los (loss of signal) detection is an active high output available to the application on any of the gpio[3:0] multi-function status and control pins. it is selected for output using the gpio[3:0]_io_select and gpio[3:0]_select bi ts accessible in the gpio_control_reg_0 an d gpio_control_reg_1 registers. it is the default output of the gpio0 pin. los indicates when the serial di gital signal selected by the in put selector is invalid. this function is always active. two methods can be used to detect loss of signal: strength (default) and edge. either method can be selected with los_detectio n_method bits of register pll_control. when strength detection is used as the method of los detection the corresponding gpio pin will be high (signal lost) when the input signal amplitude within a predefined window falls below the threshold set by the bits ddi[0:3]_los_threshold_control in the los_control_reg_1 and los_contro l_reg_2 registers. the los threshold hysteresis can be set by the los_hysteresis bits in the los_co ntrol_reg_0 register at address f h . the corresponding gpio pin will be low (signal present) when the input signal amplitude within a predefined wind ow is above the defined threshold.
GS6150 final data sheet rev.2 pds-060127 march 2015 20 of 64 proprietary & confidential www.semtech.com the method of strength detection is measurement of the average rectified differential voltage on the input pins. the strength detection method is therefore inherently dependent on the input signal's eye shape, particularly the rise/fall times of the input signal relative to the data rate. additional ly, the circuit has a lower bandwidth limit of operation (20mb/s) below whic h it is recommended that th e edge detection method is used. the absolute value of the threshold can be determined for any input swings according to equation 4-1 below: equation 4-1 where device_specific_los_threshold sp ecifies the los threshold value for a 100mv input swing at sd-rate sp ecific to each device. the ot her rates scale according to the fractional relationship given in figure 4-1 and figure 4-2 below. figure 4-1: los threshold at 100mv input swing vs. low frequency rates for a nominal device_specific_los_threshold of 53 note: edge detection method is recomm ended for signals in shaded areas. threshold 1.9 mv ddi[0..3]_los_threshold_control ) ( 53 device_specific_los_threshold () ------------------------------------------------------------------------------------------------------------------------------- --------- - = 30 35 40 45 50 55 60 0 20 40 60 80 100 120 100mv los threshold setting frequency (mb/s)
GS6150 final data sheet rev.2 pds-060127 march 2015 21 of 64 proprietary & confidential www.semtech.com figure 4-2: los threshold at 100mv input swing vs. sdi data rates for a nominal device_specific_los_threshold of 53 strength detection is unaffe cted by the trace eq settings in input_control_reg_0. when edge detection is used as the method of los detection th e corresponding gpio pin will be high (signal lost) when no transitions are detected on the selected input. the corresponding gpio pin will be low (signal present) when transitions are detected on the input. the los status is also availa ble through the los bit in the pll_status register, and as a sticky st atus through the los_sticky bit in the sticky_status register at address 50 h . 4.3.2 lock detection the GS6150 lock detection circuitry outputs a locked status signal which indicates that the cdr has achieved phase lock to the incoming data stream. the locked signal is an active high output available to the applic ation on any of the gpio[3:0] multi-function status and control pins. it is selected fo r output using the gpio[3:0]_io_select and gpio[3:0]_select bits accessible in the gpio_control_reg_0 and gpio_control_reg_1 regist ers. by default, locked is output on gpio1. the locked status is available from the locked bit in the pll_status register, and the lock_lost_sticky bit in the sticky_status register indicates wh ether lock has been lost since the bit was last cleared. to optimize systems with high dcd and/or hi gh residual isi the lock_sample bit of the pd_control register should be set to 1 b in conjunction with reducing the loop bandwidth. 6g-sdi 3g-sdi hd-sdi sd-sdi 30 35 40 45 50 55 60 0 1.485 2.97 4.455 5.94 100mv los threshold setting frequency (gb/s)
GS6150 final data sheet rev.2 pds-060127 march 2015 22 of 64 proprietary & confidential www.semtech.com 4.3.2.1 synchronous and as ynchronous lock time asynchronous lock time is defined as the time it takes the device to lock when a signal is first applied to the serial digital in puts, or when the si gnal rate changes. the synchronous lock time is defined as the ti me it takes the device to lock to a signal which has been momentarily interrupted. the asynchronous and synchronous lock times are defined in table 2-3: ac electrical characteristics . to qualify for synchronous lock time, the maximum interruption time of the signal is 10s for a 270mb/s signal. 1.485gb/s, 2.97gb/s, and 5.94gb/s signals, as well as their f/1.001 components have a maximum interruption time of 6s. the new signal, after interruption, must have the sa me frequency as the original signal but can have arbitrary phase. 4.3.3 rate detection the GS6150 can be manually forced to lock to a specific supported data rate, or automatically search for and lo ck to supported rates. the selection between manual and automatic rate selection is th rough the force_pll_rate and force_pll_rate_enable bits of the pll_control register at address 4c h . by default the device is set to automatically search for supported sdi rates. when set to automatically de tect supported data rates, the device repeatedly cycles through each supported rate that is enabled through the rate_enable_5g94, rate_enable_2g97, rate_enable_1g485, rate_enable_270m and rate_enable_125m bits of the pll_control register, until the de vice phase locks to one of the enabled rates. if lock is lost the rate search resumes, co ntinuously testing for each rate in sequence until lock is regained. the device reports the current data rate setting of the automatic rate search state machine through the detected_rate bits in the pll_status register at address 4f h . each bit of detected_rate is also avai lable to output through the gpio pins, selected for output using the gpio[3:0 ]_io_select and gpio [3:0]_select bits accessible in the gpio_con trol_reg_0 register. the supported rates that the detected_rate bits can output are shown in table 4-2 below. table 4-2: automatic rate detection - supported data rates detected_rate data rate 000 125mb/s C madi 001 270mb/s C sd 010 1.485gb/s C hd 011 2.97gb/s C 3g 100 5.94gb/s C 6g
GS6150 final data sheet rev.2 pds-060127 march 2015 23 of 64 proprietary & confidential www.semtech.com 4.3.4 low/high bit rate detection for slew rate control a status output named lbr_hbr is provided to control the slew rate selection input of a downstream sdi cable driver. it can be co nnected to the sd_en in put of drivers such as the gs6080 or gs6081 using the semtech recommended application circuit. when this signal is high, the data rate is 270mb/s (sd) or 125mb/s (madi). this signal is low for all other supported data rates, an d when the GS6150 is operating in bypass mode or any time the device is not locked. the lbr_hbr output signal is available to the application on any of the gpio[3:0] multifunction status and control pins. it is selected for output using the gpio[3:0]_io_select an d gpio[3:0]_select bits accessible in the gpio_control_reg_0 and gpio _control_reg_1 registers. by default, lbr_hbr is output on gpio2. 4.4 low power modes the device can be programmed via the gspi to operate in two different low power modes. sleep mode has minimum power consum ption at the expense of recovery time upon de-assertion of the force_pwrdn_sleep bit. standby mode has higher power consumption relative to sleep mode but mini mizes time to return to operation on de- assertion of the force_pwrdn_standby bit. the features affected by each mode are outlined below. sleep mode: ? los detection remains functional ? the gspi remains functional ? the reference oscillator remains functional standby mode: ? los detection remains functional ? the gspi remains functional ? the reference oscillator remains functional ? the vco and pll remains functional so as to minimize the lock time when a signal is detected ? the rate detector remains set to the last va lid data rate. on detection of a signal, the last valid rate is tested first by the rate detect state machine the device can be programmed to automatically enter in to sleep or standby mode when los is asserted by programmin g the auto_pwrdn_dis able bit in the pwrdn_control register at address 17 h . the auto_pwrdn_mod e bit in the same register selects which mode, sl eep or standby, is entered into upon assertion of los.
GS6150 final data sheet rev.2 pds-060127 march 2015 24 of 64 proprietary & confidential www.semtech.com 4.5 serial data output the GS6150 has two current-mode differential output drivers, each capable of driving up to 1v pp differential into an external 100 differential load. the output drivers operate with any binary coded signal with supported data rates up to 5.94gb/s. this is applicable to both the serial data (ddo, ddo ) and serial data (ddo1, ddo1 ) outputs of the device. 4.5.1 output impedance each of the GS6150s output buffers incl ude two on-chip, 50 termination resistors. 4.5.2 output signal interface levels the serial digital outputs oper ate within specification with an output cml power supply of 1.2v to 2.5v. 4.5.3 adjustable output swing through the gspi, the output swing can be set in the range from approximately 230mv ppd to 930mv ppd in 45mv ppd increments, when the outputs are terminated with 50 loads. for the exact values, please see table 4-3 below. the output swing for each data rate is controlled using the bits in the driver_control_reg_3, dr iver_control_reg_4, driv er_control_reg_5, and driver_control_reg_6 re gisters at addresses 1c h through 1f h . the device automatically adjusts the swing se tting depending on the state of the device (i.e. detected rate, bypass mode, or mute). there are separate register controls for mute, bypass and each data rate. table 4-3: serial digita l output swing settings register setting (see note 1 ) min typ max units 0000 b 175 230 290 mv 0001 b 205 275 345 mv 0010 b 245 325 405 mv 0011 b (default) 280 370 460 mv 0100 b 310 410 510 mv 0101 b 345 460 575 mv 0110 b 380 510 640 mv 0111 b 420 560 700 mv
GS6150 final data sheet rev.2 pds-060127 march 2015 25 of 64 proprietary & confidential www.semtech.com 4.5.4 output de-emphasis the GS6150 features adjustable output de-emphasis to compensate for pcb dielectric trace loss. each output can be independentl y set to a different de -emphasis setting for each detected rate through controls found in the driver_control_reg_1 and driver_control_r eg_2 registers. the effect of de-emph asis, illustrated in figure 4-3 , is to attenuate the swing of bits that do not follow a bit transition (v de ). the swing of bits that do follow a bit transition (v nom ) is set by the output sw ing registers found in section 4.5.3 and do not depend on the de-emphasis settings. figure 4-3: de-emphasis waveform 1000 b 455 605 760 mv 1001 b 490 655 820 mv 1010 b 530 705 880 mv 1011 b 565 755 945 mv 1100 b 600 800 1000 mv 1101 b 630 840 1050 mv 1110 b 670 890 1110 mv 1111 b 700 930 1160 mv note: 1. applicable registers that can be programmed with the values shown above are ddo0_swing_1g485, ddo0_swing_270m, ddo0_swing_125m, ddo0_swing_bypass, ddo0_swing_mute, ddo0_swing_5g94, ddo0_swing_2g97, ddo1_swing_1g485, ddo1_swing_270m, ddo1_swing_125m, ddo1_swing_bypass, ddo1_swing_mute, ddo1_swing_5g94, and ddo1_swing_2g97 table 4-3: serial digital outp ut swing settings (continued) register setting (see note 1 ) min typ max units nominal swing (v nom ) de-emphasized swing (v de ) de-emphasis = 20 x log 10 (v nom / v de ) 0 data pattern 111 00
GS6150 final data sheet rev.2 pds-060127 march 2015 26 of 64 proprietary & confidential www.semtech.com the default de-emphasis settings for each rate are given in th e register descriptions for driver_control_reg_1 and driver_control_reg_2 in table 5-1 . de-emphasis is disabled on both outputs in bypass mode, when the output is muted, or when the device is not locked. 4.5.5 output common mode voltage the output common mode voltage level (v cmout ) is a function of the output voltage swing, the output dr iver supply voltage (v cc_ddo ) and how the transmission line is terminated. if the outputs are terminated through 50 resistors to a voltage v term equal to v cc_ddo , as shown in figure 4-5 below, the output common mode voltage is given by the foll owing expression: equation 4-2 if the differential outputs are terminated across a 100 resistor, as shown in figure 4-4 below, the output common mode voltage is given by the fo llowing expression: equation 4-3 4.6 output mute, disable, and data selection the GS6150 outputs can each be individ ually muted using the ddo0_mute and ddo1_mute bits in the driver_contr ol_reg_0 register at address 19 h . each output can also be independently disabled through either register or gpio control. when disabled each pin of the output is pulled to v cc_ddo . register driver_control_reg_0 contai ns both register based di sable bits (ddo0_disable, ddo1_disable) and bits for selection between register and gpio control (ddo0_disable_select, ddo1_disable_se lect). for gpio control refer to section 4.10 . v cmout v cc_ddo v ddo 4 ------------------- - ? = v cmout v cc_ddo v ddo 2 ------------------- - ? = figure 4-4: 100 parallel output termination figure 4-5: 50 termination to v term 100 50 50 50 50 ddo vcc_ddo 50 50 dd o v cc_ddo GS6150 ddo 50 50 ddo vcc_ddo 50 50 dd o v cc_ddo 50 50 GS6150 v term v term 50 50 ddo
GS6150 final data sheet rev.2 pds-060127 march 2015 27 of 64 proprietary & confidential www.semtech.com by default ddo0, ddo0 is enabled/disabled through register control and set to enabled. ddo1, ddo1 is enabled/disabled through gpio3 and set to output data. 4.7 bypass mode in cdr bypass mode, the GS6150 passes the in put data to the outputs, bypassing the retiming functionality. there are two bits in the control regi sters that control the bypass function: manual_bypass and auto_bypass in the reclocker_bypass register at address 20 h . the manual_bypass bit is inactive (set to 0) by default. the auto_bypass bit is active (set to 1) by default, and places the GS6150 reclocker into bypass mode when the pll is not locked to a data rate. the bypass function does no t affect the trace equalization function of the device. note: if manual_bypass is active, it ov errides the auto_b ypass bit setting. 4.8 dvb-asi the GS6150 has the ability to reclock dvb-asi signals at 270mb/s. all relevant settings and control registers that apply to sd-sdi si gnals at 270mb/s are al so compatible with dvb-asi signals at 270mb/s. 4.9 device power up 4.9.1 power on reset (por) the GS6150 features an on-chip power-on-reset that places all registers and internal state machines into their known, default states when the chip is powered up. 4.9.2 reset pin (rst ) when the rst pin is set low, all functional blocks are set to their defa ult conditions and high-speed data and digital functionality is suspended. when it is set high, normal operation of the device resumes 0.5ms after the low-to-high transition of the signal. this pin is not required at powe r up and may be left unconnected. 4.10 gpio pins configuration the GS6150 has four gpio pins that can ea ch be configured as outputs for various internal status signals, or as inputs to di sable either output-drive r through pin control. the bits gpio[0:3]_io_select are used to co nfigure the gpio pins as outputs (0) or inputs (1). the signals that are output or input on the gpio pins are selected on gpio_control_reg_0 and gpio _control_reg_1. the signals that can be output on the gpio pins are listed in table 4-4 below.
GS6150 final data sheet rev.2 pds-060127 march 2015 28 of 64 proprietary & confidential www.semtech.com the signals that can be input on the gpios are listed in table 4-5 below. by default, the gpio pins are conf igured to the foll owing parameters: gpio0: los (output) gpio1: locked (output) gpio2: lbr_hbr (output) gpio3: ddo1_disable (input) table 4-4: gpio status outputs gpio[0:3]_select parameter description 0000 los loss of signal indication - high when there is no detected signal on the selected ddi input 0001 locked phase lock indication - high when the cdr has phase- locked to a valid input signal 0010 lbr_hbr low bit-rate/high bit-rate - high when the part is locked to the sd data rate; low for all other data rates and in bypass. 0101 rate_det0 rate detect - three bits used in conjunction that represent the data rate detected by the rate search state machine. refer to table 4-2 for rate encoding details. 0110 rate_det1 0111 rate_det2 1000 locked_125m high when the rate search state machine is locked to a madi data rate (125mb/s) 1001 locked_270m high when the rate search state machine is locked to an sd data rate (270mb/s) 1010 locked_1g485 high when the rate search state machine is locked to an hd data rate (1.485gb/s) 1011 locked_2g97 high when the rate search state machine is locked to a 3g data rate (2.97gb/s) 1100 locked_5g94 high when the rate search state machine is locked to a 6g data rate (5.94gb/s) 1101 rate_change when a change in the data rate is detected by the rate search state machine, the rate_change signal is pulsed high for a duration of 37ns table 4-5: gpio signal inputs gpio[0:3]_select parameter description 0000 ddo0_disable disables serial data output 0 (ddo0 , ddo0) 0001 ddo1_disable disables serial data output 1 (ddo1 , ddo1)
GS6150 final data sheet rev.2 pds-060127 march 2015 29 of 64 proprietary & confidential www.semtech.com 4.11 gspi host interface the GS6150 is controlled via the gennum serial peripheral interface (gspi). the gspi host interface is comprised of a seri al data input signal (s din pin), serial data output signal (sdout pin), an active-low chip select (cs pin) and a burst clock (sclk pin). the GS6150 is a slave device, therefore the sclk, sdin and cs signals must be sourced by the application host processor. all read and write access to the device is in itiated and terminated by the application host processor. it is strongly recommended to connect the gspi pins of the GS6150 to a host/system processor/controller or fpga to facilitate optimization of the device to meet specific application requirements. modi fication of many device settings is only facilitated through the gspi of the GS6150, and is not available on external pins. 4.11.1 cs pin the chip select pin (cs ) is an active-low si gnal provided by the host processor to the GS6150. the high-to-low transition of this pin marks the start of serial communication to the GS6150. the low-to-high transition of this pin mark s the end of serial communication to the GS6150. there is an option for each device to use a separate unique chip select signal from the host processor or for up to 32 devices to be connected to a single chip select when making use of the unit address feature. only those devices whose unit address matches the unit address in the gspi command word will respond to communicat ion from the host processor (unless the bcast all bit in the gspi command word is set to 1). 4.11.2 sdin pin the sdin pin is the gspi serial data input pin of the GS6150. the 16-bit command and data words from the host processor or from the sdout pin of other devices are shifted into the device on the rising edge of sclk when the cs pin is low. 4.11.3 sdout pin the sdout pin is the gspi serial data output of the GS6150. all data transfers out of the GS6150 to the host processor or to the sdin pin of other connected devices occur from this pin. by default at power up or after system reset, the sdout pin provides a non-clocked path directly from the sdin pin, regardless of the cs pin state, except during the gspi data
GS6150 final data sheet rev.2 pds-060127 march 2015 30 of 64 proprietary & confidential www.semtech.com word portion for read operations to the de vice. this allows multiple devices to be connected in loop-through configuration. for read operations, the sdout pin is used to output data read from an internal configuration and status register (csr) when cs is low. data is shifted out of the device on the falling edge of sclk, so that it can be read by the host processor or other downstream connected device on th e subsequent sclk rising edge. 4.11.3.1 gspi link disable operation it is possible to disable the direct sdin to sdout (loop-through) connection by writing a value of 1 to the gspi_link_disable bit in register_0. when disabled, any data appearing at the sdin pin will not appear at the sdout pin and the sdout pin is high. note: disabling the loop-through operation is temporarily required when initializing the unit address for up to 32 connected devices. the time required to enable/disable the lo op-through operation from assertion of the register bit is less than the gspi config uration command delay as defined by the parameter t cmd_gspi_config (5 sclk cycles). figure 4-6: gspi_link_disable operation 4.11.3.2 gspi bus-th rough operation using gspi bus-through operation, the GS6150 can share a common pcb trace with other gspi devices for sdout output. when configured for bus-th rough operation, by setting gspi_bus_through_enable bit to 1, the sdout pin will be high-impedance when the cs pin is high. when the cs pin is low, the sdout pin will be driven and will follow regular read and write operation as described in section 4.11.3 . table 4-6: gspi_link_disable bit operation bit state description 0 sdin pin is looped through to the sdout pin 1 data appearing at sdin does not appe ar at sdout, and sdout pin is high. sdin pin sdout pin gspi_link _disable bus_through cs pin high-z configuration and status register
GS6150 final data sheet rev.2 pds-060127 march 2015 31 of 64 proprietary & confidential www.semtech.com multiple chains of GS6150 devices can share a single sdout bus connection to host by configuring the devices for bus-through operation. in such configuration, each chain requires a separate chip select (cs ). figure 4-7: gspi_bus_through_enable operation 4.11.4 sclk pin the sclk pin is the gspi serial data shift cl ock input to the device, and must be provided by the host processor. serial data is clocked into the GS6150 sdin pin on the rising edge of sclk. serial data is clocked out of the device fr om the sdout pin on the falling edge of sclk (read operation). sclk is ignored when cs is high. the maximum interface clock rate is 27mhz. 4.11.5 command word description all gspi accesses are a minimum of 32 bits in length (a 16-bit command word followed by a 16-bit data word) and the start of ea ch access is indicated by the high-to-low transition of the chip select (cs ) pin of the GS6150. the format of the command word and data words are shown in figure 4-8 . data received immediatel y following this high-to-low tran sition will be interpreted as a new command word. 4.11.5.1 r/w bit - b15 command word this bit indicates a read or write operation. when r/w is set to 1, a read operation is indica ted, and data is read from the register specified by the address field of the command word. when r/w is set to 0, a write operation is indica ted, and data is written to the register specified by the address field of the command word. sdin pin sdout pin gspi_link _disable bus_through cs pin high-z configuration and status register
GS6150 final data sheet rev.2 pds-060127 march 2015 32 of 64 proprietary & confidential www.semtech.com 4.11.5.2 b'cast all - b14 command word this bit is used in write operations to co nfigure all devices conn ected in loop-through and bus-through configuratio n with a single command. when bcast all is set to 1, the followin g data word (autoinc = 0) or data words (autoinc = 1) are written to the register specified by the address field of the command word (and subsequent addresses when autoinc = 1), regardless of the setting of the unit address(es). when bcast all is set to 0, a normal writ e operation is indicate d. only those devices that have a unit address ma tching the unit address fiel d of the command word write the data word to the regist er specified by the address field of the command word. 4.11.5.3 emem - b13 command word when the emem bit is 1 the address word is extended to 23 bits to allow access to registers located in the extended memory space. when the emem bit is 0, the address word is limited to 7 bits. 4.11.5.4 autoinc - b12 command word when autoinc is set to 1, auto-increment read or write access is enabled. in auto-increment mode, the device automati cally increments the register address for each contiguous read or write access, starti ng from the address de fined in the address field of the command word. the internal address is increm ented for each 16-bit read or write access until a low-to- high transition on the cs pin is detected. when autoinc is set to 0, single read or write access is required. auto-increment write must not be used to update values in host_config. 4.11.5.5 unit address - b11:b7 command word the 5 bits of the unit address field of the command word are used to select one of 32 devices connected on a single chip select in loop-through or bus-through configurations. read and write accesses are only accepted if the unit address field matches the programmed device_unit_address in host_config. by default at power-up or after a device re set, the device_unit_address is set to 00h 4.11.5.6 address - b6:b0 command word if the extended memory is not being accessed (emem = 0), the 7 bits of the address field are used to select one of 128 register addresses in the device in single read or write access mode, or to set the starting address for read or write accesses in auto-increment mode.
GS6150 final data sheet rev.2 pds-060127 march 2015 33 of 64 proprietary & confidential www.semtech.com figure 4-8: command and data word format when emem is set to 1, the address word is extended to 23 bits. the command and data word format will be extended by another 16 bits, and is shown in figure 4-9 below. figure 4-9: command and data word format with emem set to 1 msb lsb r / w emem autoinc a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a11 a10 command word unit address address b?cast all d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 data word 7-bit csr address field providing up to 128 configuration registers. 5-bit unit address field providing up to 32 devices to be connected on a single cs. auto increment read/write access when set. single read write access when reset. extended memory mode. when set, the extended memory mode is enabled. when reset, normal gspi addressing is enabled. read access when this bit is set. write access when this bit is reset. when set, the unit address field is ignored and all data accesses are actioned by the device. when reset, the unit address is used to manage data accesses in the device. msb lsb r / w emem autoinc a7 a8 a9 a11 a10 command word unit address address[22:16] b?cast all d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 data word address[15:0] a16 a17 a18 a19 a20 a21 a22 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15
GS6150 final data sheet rev.2 pds-060127 march 2015 34 of 64 proprietary & confidential www.semtech.com 4.11.6 gspi transaction timing figure 4-10: gspi exte rnal interface timing x t cmd_gspi_config t cmd t 9 sclk sdout sdin x cs r /w bcst sclk write mode sdi signal is looped out on sdo sdout emem auto _inc a4 a3 a2 a1 a0 r /w bcst sdin emem auto _inc ua4 ua3 ua2 ua1 ua0 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 t 0 t 8 t 2 t 3 t 1 t 7 t 4 a6 a5 ua4 ua3 ua2 ua1 ua0 a6 a5 cs r/w rsv read mode sdi signal is looped out on sdo emem auto _inc a4 a3 a2 a1 a0 read data is output on sdo d0 r/w rsv emem auto _inc a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d15 d14 d13 d12 d11 d10 d9 d8 t 9 t 6 t 5 ua4 ua3 ua2 ua1 ua0 a6 a5 ua4 ua3 ua2 ua1 ua0 a6 a5 sclk sdout sdin cs table 4-7: gspi timing parameters parameter symbol equivalent sclk cycles (at 27mhz) min typ max units sclk frequency 27 mhz cs low before sclk rising edge t 0 2.0 ns sclk period t 1 37 ns sclk duty cycle t 2 40 50 60 % input data setup time t 3 2.7 ns sclk idle time -write t 4 137ns sclk idle time - read t 5 5 161.0 ns
GS6150 final data sheet rev.2 pds-060127 march 2015 35 of 64 proprietary & confidential www.semtech.com inter-command delay time t cmd 4 120.0 ns inter-command delay time (after gspi configuration write) t cmd_gspi_ conf 1 5 162.0 ns sdo after sclk falling edge t 6 7.5ns cs high after final sclk falling edge t 7 0.0 ns input data hold time t 8 1.0 ns cs high time t 9 57.0 ns sdin to sdout combinational delay 5.0ns max. chips daisy chained at max sclk frequency when host clocks in sdout data on rising edge of sclk 1 GS6150 chips max. frequency for 32 daisy-chained devices 2.1mhz max. chips daisy-chained at max. sclk frequency when host clocks in sdout data on falling edge of sclk 3 GS6150 chips max. frequency for 32 daisy-chained devices 2.2mhz note: 1. t cmd_gspi_conf inter-command delay must be used whenever modifying host_config register at address 0x00 table 4-7: gspi timing parameters (continued) parameter symbol equivalent sclk cycles (at 27mhz) min typ max units
GS6150 final data sheet rev.2 pds-060127 march 2015 36 of 64 proprietary & confidential www.semtech.com 4.11.7 single read/write access single read/write access timing fo r the gspi interface is shown in figure 4-11 to figure 4-15 . when performing a single read or write access, one data word is read from/written to the device per access. each access is a mi nimum of 32-bits long, consisting of a command word and a single data word. the read or write cycle begins with a high-to- low transition of the cs pin. the read or write access is terminated by a low-to-high transition of the cs pin. the maximum interface clock rate is 27 mhz and the inter-command delay time indicated in the figures as t cmd , is a minimum of 4 sclk clock cycles. after modifying values in host_config, the inter-command delay time, t cmd_gspi_config , is a minimum of 5 sclk clock cycles. for read access, the time from the last bit of the command word to the start of the data output, as defined by t 5 , corresponds to no less than 5 sclk clock cycles at 27mhz. figure 4-11: gspi write timing C single write access with l oop-through operation (default) figure 4-12: gspi write timi ng C single write access with gspi link-disable operation figure 4-13: gspi write timing C single write access with bus-through operation sclk cs sdin sdout command command data data command command x x cmd t sclk cs sdin sdout command data command x cmd t sclk cs sdin sdout command command data data command command x high-z cmd t high-z
GS6150 final data sheet rev.2 pds-060127 march 2015 37 of 64 proprietary & confidential www.semtech.com figure 4-14: gspi read timing C single read access with loop-through operation (default) figure 4-15: gspi read timing C single read access with bus-through operation 4.11.8 auto-increment read/write access auto-increment read/write access timing for the gspi interface is shown in figure 4-16 to figure 4-20 . auto-increment mode is enab led by the setting of the autoinc bit of the command word. in this mode, multiple data words can be read from/written to th e device using only one starting address. each access is initiated by a high-to-low transition of the cs pin, and consists of a command word and one or more data words. the internal address is automatically incremen ted after the first read or writ e data word, and continues to increment until the read or wr ite access is terminated by a low-to-high transition of the cs pin. note : writing to host_config using auto -increment access is not allowed. the maximum interface clock rate is 27 mhz and the inter-command delay time indicated in the diagram as t cmd , is a minimum of 4 sclk clock cycles. for read access, the time from the last bit of the first command word to the start of the data output of the first data word as defined by t 5 , will be no less than 5 sclk cycles at 27mhz. all subsequent read da ta accesses will not be subjec t to this delay during an auto-increment read. figure 4-16: gspi write timing C auto-incre ment with loop-through operation (default) sclk cs sdin sdout command command data 5 t sclk cs sdin sdout command command data 5 t x high-z high-z sclk cs sdin sdout command command data 1 data 1 data 2 data 2
GS6150 final data sheet rev.2 pds-060127 march 2015 38 of 64 proprietary & confidential www.semtech.com figure 4-17: gspi write timing C auto-inc rement with gspi li nk disable operation figure 4-18: gspi write timing C auto-increment with bus-through operation figure 4-19: gspi read timing C auto-increme nt read with loop-thr ough operation (default) figure 4-20: gspi read timing C auto-inc rement read with bu s-through operation 4.11.9 setting a device unit address multiple (up to 32) GS6150 devices can be connected to a common chip select (cs ) in loop-through or bus-through operation. to ensure that each device selected by a common cs can be separate ly addressed, a unique unit address must be programmed by the host proce ssor at start-up as part of system initialization or following a device reset. note: by default at power up or after a device reset, the de vice_unit_address of each device is set to 0h and the sdin->sdout no n-clocked loop-through for each device is enabled. these are the steps required to set the device_unit_address of devices in a chain to values other than 0: 1. write to unit address 0 selecting host_config (address = 0), with the gspi_link_disable bit set to 1 and the de vice_unit_address field set to 0. this disables the direct sdin->sdout non-clocke d path for all devices on chip select. sclk cs sdin sdout command data 1 data 2 sclk cs sdin sdout command command data 1 data 1 data 2 data 2 high-z sclk cs sdin sdout 5 t command command data 1 data 2 sclk cs sdin sdout 5 t command command data 1 data 2 high-z x
GS6150 final data sheet rev.2 pds-060127 march 2015 39 of 64 proprietary & confidential www.semtech.com 2. write to unit address 0 selecting host_config (address = 0), with the gspi_link_disable bit set to 0 and th e device_unit_address field set to a unique unit address. this configures de vice_unit_address for the first device in the chain. each subsequent such write to unit address 0 will configure the next device in the chain. if there are 32 devices in a chain, the last (32nd) device in the chain must use device_unit_address value 0. 3. repeat step 2 using new, unique valu es for the device_unit_address field in host_config until all devices in the chain have been configured with their own unique unit address value. note: t cmd_gspi_conf delay must be observed after every write that modifies host_config. all connected devices receive this command (by default the unit address of all devices is 0), and the loop-through operation will be re-established for all connected devices. once configured, each device will on ly respond to command words with a unit address field matching the de vice_unit_address in host_config note: although the loop-through and bus-through configurations are compatible with previous generation gspi enabled devic es (backward compatibility), only devices supporting unit addressing can share a chip select. all devices on any single chip select must be connected in a contiguous chain with only the last device's sdout connected to the application host processor. multiple chains configured in bus-through mode can have their final sdout outputs connected to a single application host processor input. 4.11.10 default gspi operation by default at power up or after a device re set, the GS6150 is set for loop-through operation and the internal device_unit_a ddress field of the device is set to 0. figure 4-21 shows a functional block diagram of th e configuration and status register (csr) map in the GS6150 for non-ex tended memory accesses (emem = 0). figure 4-21: internal register map functional block diagram [12] [6:0] reg 0 compare configuration and status registers read/write reg 1 reg 128 cmd at power-up or after a device reset, device_unit_address = 00h data to be written / read data data [15:0] [11:7] [13] [14] bits local address r / w unit address bcast all auto inc emem [15] device_unit_address gspi_link _disable gspi_bus_ through _enable reserved bits [4:0] [13] [14] [15] 32 devices 128 registers bits reserved [12:5]
GS6150 final data sheet rev.2 pds-060127 march 2015 40 of 64 proprietary & confidential www.semtech.com the steps required for the application host processor to write to the configuration and status registers via the gspi, are as follows: 1. set command word for write access (r/w = 0) to the local registers 0h-80h; set auto increment; set the unit address fiel d in the command word to match the configured device_unit_address which will be zero. write the command word. 2. write the data word to be written to the first register. 3. write the data word to be written to the next register in auto increment mode, etc. read access is the same as the above with the exception of step 1, where the command word is set for read access (r/w = 1). note: the unit address field of the command word must always match device_unit_address for an access to be accepted by the device. changing device_unit_address to a value other than 0 is only required if multiple devices are connected to a single chip select (in lo op-through or bus-through configuration.)
GS6150 final data sheet rev.2 pds-060127 march 2015 41 of 64 proprietary & confidential www.semtech.com 5. host interface register map table 5-1: register descriptio ns - standard address space address register name parameter name bit slice r/w reset value description 0 h host_config rsvd 15:15 rw 0 h reserved. do not change. gspi_link_disable 14:14 rw 0 h gspi loop-through disable. gspi_bus_through_ enable 13:13 rw 0 h gspi bus-through enable. rsvd 12:5 rw 0 h reserved. do not change. device_unit_address 4:0 rw 0 h device address programmed by application. 1 h device_info rsvd 15:8 ro 1 h reserved. device_version_id 7:0 ro - device version identifier. 2 h gpio_control_ reg_0 rsvd 15:14 rw 0 h reserved. do not change. gpio1_io_select 13:13 rw 0 h gpio1 input/output select 0 b : output 1 b : input rsvd 12:11 rw 0 h reserved. do not change. gpio1_select 10:7 rw 1 h gpio1 signal selection if gpio1_io_select is set to 0: 0000 b : los 0001 b : locked (default) 0010 b : lbr_hbr 0011 b : reserved 0100 b : reserved 0101 b : rate_det0 0110 b : rate_det1 0111 b : rate_det2 1000 b : locked_125m 1001 b : locked_270m 1010 b : locked_1g485 1011 b : locked_2g97 1100 b : locked_5g94 1101 b : rate_change if gpio1_io_select is set to 1: 0000 b : ddo0_disable 0001 b : ddo1_disable gpio0_io_select 6:6 rw 0 h gpio0 input/output select 0 b : output 1 b : input rsvd 5:4 rw 0 h reserved. do not change.
GS6150 final data sheet rev.2 pds-060127 march 2015 42 of 64 proprietary & confidential www.semtech.com 2 h gpio_control_ reg_0 gpio0_select 3:0 rw 0 h gpio0 signal selection if gpio0_io_select is set to 0: 0000 b : los (default) 0001 b : locked 0010 b : lbr_hbr 0011 b : reserved 0100 b : reserved 0101 b : rate_det0 0110 b : rate_det1 0111 b : rate_det2 1000 b : locked_125m 1001 b : locked_270m 1010 b : locked_1g485 1011 b : locked_2g97 1100 b : locked_5g94 1101 b : rate_change if gpio0_io_select is set to 1: 0000 b : ddo0_disable 0001 b : ddo1_disable table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 43 of 64 proprietary & confidential www.semtech.com 3 h gpio_control_ reg_1 rsvd 15:14 rw 0 h reserved. do not change. gpio3_io_select 13:13 rw 1 h gpio3 input/output select 0 b : output 1 b : input rsvd 12:11 rw 0 h reserved. do not change. gpio3_select 10:7 rw 1 h gpio3 signal selection if gpio3_io_select is set to 0: 0000 b : los 0001 b : locked 0010 b : lbr_hbr 0011 b : reserved 0100 b : reserved 0101 b : rate_det0 0110 b : rate_det1 0111 b : rate_det2 1000 b : locked_125m 1001 b : locked_270m 1010 b : locked_1g485 1011 b : locked_2g97 1100 b : locked_5g94 1101 b : rate_change if gpio3_io_select is set to 1: 0000 b : ddo0_disable 0001 b : ddo1_disable (default) gpio2_io_select 6:6 rw 0 h gpio2 input/output select 0 b : output 1 b : input table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 44 of 64 proprietary & confidential www.semtech.com 3 h gpio_control_ reg_1 rsvd 5:4 rw 0 h reserved. do not change. gpio2_select 3:0 rw 2 h gpio2 signal selection if gpio2_io_select is set to 0: 0000 b : los 0001 b : locked 0010 b : lbr_hbr (default) 0011 b : reserved 0100 b : reserved 0101 b : rate_det0 0110 b : rate_det1 0111 b : rate_det2 1000 b : locked_125m 1001 b : locked_270m 1010 b : locked_1g485 1011 b : locked_2g97 1100 b : locked_5g94 1101 b : rate_change if gpio2_io_select is set to 1: 0000 b : ddo0_disable 0001 b : ddo1_disable 4 h reserved rsvd 15:0 rw 1c h reserved. do not change. 5 h input_control_ reg_0 ddi3_trace_eq_control 7:6 rw 0 h ddi3 trace-eq configuration 00 b : off 01 b : 0db/eq bypass 10 b : low 11 b : high ddi2_trace_eq_ control 5:4 rw 0 h ddi2 trace-eq configuration 00 b : off 01 b : 0db/eq bypass 10 b : low 11 b : high ddi1_trace_eq_ control 3:2 rw 0 h ddi1 trace-eq configuration 00 b : off 01 b : 0db/eq bypass 10 b : low 11 b : high ddi0_trace_eq_ control 1:0 rw 0 h ddi0 trace-eq configuration 00 b : off 01 b : 0db/eq bypass 10 b : low 11 b : high table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 45 of 64 proprietary & confidential www.semtech.com 6 h reserved rsvd 15:0 rw 0 h reserved. do not change. 7 h input_control_ reg_2 rsvd 15:12 rw 0 h reserved. do not change. ddi_select 11:10 rw 0 h input selection 00 b : ddi0 01 b : ddi1 10 b : ddi2 11 b : ddi3 used when input_selection_control is set to 01 b or 11 b input_selection_control 9:8 rw 0 h determines the source for the input selection block. x0 b : use ddi_sel0_strobe and ddi_sel1 pins. 01 b : use ddi_select bits 11 b : use ddi_select bits; update occurs on low-to-high transition of ddi_sel0_strobe pin. ddi3_trace_eq_dc_term_ enable 7:7 rw 1 h enable ddi3 on-chip trace-eq dc termination. 0 b : disabled 1 b : enabled ddi2_trace_eq_dc_term_ enable 6:6 rw 1 h enable ddi2 on-chip trace-eq dc termination. 0 b : disabled 1 b : enabled ddi1_trace_eq_dc_term_ enable 5:5 rw 1 h enable ddi1 on-chip trace-eq dc termination. 0 b : disabled 1 b : enabled ddi0_trace_eq_dc_term_ enable 4:4 rw 1 h enable ddi0 on-chip trace-eq dc termination. 0 b : disabled 1 b : enabled rsvd 3:0 rw 0 h reserved. do not change. 8 h reserved rsvd 15:0 rocw reserved. do not change. 9 h reserved rsvd 15:0 ro reserved. a h reserved rsvd 15:0 ro reserved. b h reserved rsvd 15:0 ro reserved. c h reserved rsvd 15:0 ro reserved. table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 46 of 64 proprietary & confidential www.semtech.com d h reserved rsvd 15:0 ro reserved. e h reserved rsvd 15:0 ro reserved. f h los_control_ reg_0 rsvd 15:10 rw 0 h reserved. do not change. los_threshold_control_ enable 9:9 rw 0 h enables los threshold adjustment based on the settings in the ddi[3:0]_los_threshold_control bits in the los_control_reg_1 and los_control_reg_2 registers. 0 b : default internal thresholds are used 1 b : thresholds used in the los_control_reg_1 and los_control_reg_2 registers los_deassert_time 8:7 rw 2 h los de-assert time delay: 00 b : 2.30s 01 b : 1.50s 10 b : 1.20s 11 b : 0.90s los_assert_time 6:5 rw 2 h los assert time delay: 00 b : 68s 01 b : 64s 10 b : 62s 11 b : 61s los_hysteresis 4:1 rw 0 h los threshold hysteresis adjustment: 0000 b : 0 db 0001 b : 0.32 db 0010 b : 0.64 db 0011 b : 0.98 db 0100 b : 1.34 db 0101 b : 1.70 db 0110 b : 2.09 db 0111 b : 2.49 db 1000 b : 2.84 db 1001 b : 3.28 db 1010 b : 3.74 db 1011 b : 4.23 db 1100 b : 4.75 db 1101 b : 5.30 db 1110 b : 5.89 db 1111 b : 6.53 db los_pwrdn_override 0:0 rw 0 h override the internal power-down control for the los circuit. 0 b : los active 1 b : los powered down table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 47 of 64 proprietary & confidential www.semtech.com 10 h los_control_ reg_1 ddi1_los_threshold_ control 15:8 rw 5a h los signal threshold for input ddi1 at device pins is: 1.9mv ppd x ddi1_los_threshold_control x (53/device_specific_los_threshold) (all above values are in decimal) ddi0_los_threshold_ control 7:0 rw 5a h los signal threshold for input ddi0 at device pins is: 1.9mv ppd x ddi0_los_threshold_control x (53/device_specific_los_threshold) (all above values are in decimal) 11 h los_control_ reg_2 ddi3_los_threshold_ control 15:8 rw 5a h los signal threshold for input ddi3 at device pins is: 1.9mv ppd x ddi3_los_threshold_control x (53/ device_specific_los_threshold) (all above values are in decimal) ddi2_los_threshold_ control 7:0 rw 5a h los signal threshold for input ddi2 at device pins is: 1.9mv ppd x ddi2_los_threshold_control x (53/device_specific_los_threshold) (all above values are in decimal) 12 h los_status rsvd 15:8 ro reserved. device_specific_los_ threshold 7:0 ro trimmed setting to achieve los threshold of 100mv ppd 13 h reserved rsvd 15:0 rw 280 h reserved. do not change. 14 h reserved rsvd 15:0 ro reserved. 15 h ref_clk_ control rsvd 15:3 rw 0 h reserved. do not change. xtal_buf_out_enable 2:2 rw 1 h enables/disables the reference buffer output. 0 b : xtal_buf_out disabled 1 b : xtal_buf_out enabled rsvd 1:1 rw 0 h reserved. do not change. rsvd 0:0 rw 0 h reserved. do not change. 16 h ref_clk_status rsvd 15:1 ro reserved. xtal_clk_det 0:0 ro - indicates whether an external 27mhz reference is being used by the device or its internal oscillator. 0 b : internal oscillator being used 1 b : external crystal being used table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 48 of 64 proprietary & confidential www.semtech.com 17 h pwrdn_ control auto_pwrdn_mode 3:3 rw 0 h selects the low power mode, sleep or standby that is entered into when auto_pwrdn_disable is set to 0 and los is asserted. 0 b : sleep mode is selected (default) 1 b : standby mode is selected force_pwrdn_standby 2:2 rw 0 h forces the device into standby mode when force_pwrdn_sleep is set to 0. 0 b : device not in standby mode 1 b : device in standby mode force_pwrdn_sleep 1:1 rw 0 h forces the device into sleep mode when auto_pwrdn_disable is set to 1. 0 b : device not in sleep mode 1 b : device in sleep mode when force_pwrdn_sleep is set to 1, it takes precedence over the force_pwrdn_standby bit. auto_pwrdn_disable 0:0 rw 1 h disables auto powerdown mode which automatically enters sleep or standby mode when los is asserted. 0 b : device automatically enters sleep or standby when los is 1 1 b : device only enters sleep or standby when force_pwrdn_sleep or force_pwrdn_standby are set to 1 18 h reserved rsvd 15:0 ro reserved. table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 49 of 64 proprietary & confidential www.semtech.com 19 h driver_control_ reg_0 rsvd 15:8 rw 0 h reserved. do not change. rsvd 7:7 rw 1 h reserved. do not change. auto_los_mute_enable 6:6 rw 0 h auto-mute enable on los. 0 b : output is unaffected by los 1 b : output is muted when los is asserted ddo1_mute 5:5 rw 0 h mute control for the ddo1 output. 0 b : ddo1 output not muted 1 b : ddo1 output muted output across ddo1 and ddo1 is static and of magnitude ddo1_swing_mute/2 when ddo1_disable is set to 0. ddo0_mute 4:4 rw 0 h mute control for the ddo0 output. 0 b : ddo0 output not muted 1 b : ddo0 output muted output across ddo0 and ddo0 is static and of magnitude ddo0_swing_mute/2 when ddo0_disable is set to 0. ddo1_disable 3:3 rw 0 h disable control for the ddo1 output. 0 b : ddo1 output not disabled 1 b : ddo1 output disabled output of both ddo1 and ddo1 is vcc_ddo1. this bit takes precedence over ddo1_mute. ddo0_disable 2:2 rw 0 h disable control for the ddo0 output. 0 b : ddo0 output not disabled 1 b : ddo0 output disabled output of both ddo0 and ddo0 is vcc_ddo0. this bit takes precedence over ddo0_mute. ddo1_disable_select 1:1 rw 0 h controls whether ddo1 is disabled using an assigned gpio pin or the ddo1_disable bit. 0 b : ddo1 is disabled using assigned gpio 1 b : ddo1 is disabled using the ddo1_disable bit ddo0_disable_select 0:0 rw 1 h controls whether ddo0 is disabled using an assigned gpio pin or the ddo0_disable bit. 0 b : ddo0 is disabled using assigned gpio 1 b : ddo0 is disabled using the ddo0_disable bit table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 50 of 64 proprietary & confidential www.semtech.com 1a h driver_control_ reg_1 rsvd 15:15 rw 0 h reserved. do not change. ddo0_deemphasis_5g94 14:12 rw 2 h de-emphasis control for 5.94gb/s (6gb/s uhd-sdi) signals output on ddo0 000 b : 0db 001 b : 0.3db 010 b : 0.6db (default) 011 b : 2.3 b 100 b : 4.0db 101 b : 6.6db 110 b : 10.0db ddo0_deemphasis_2g97 11:9 rw 1 h de-emphasis control for 2.97gb/s (3gb/s sdi) signals output on ddo0 000 b : 0db 001 b : 0.4db (default) 010 b : 1.5db 011 b : 3.2db 100 b : 4.9db 101 b : 7.6db 110 b : 11.0db ddo0_deemphasis_1g485 8:6 rw 1 h de-emphasis control for 1.485gb/s (hd-sdi) signals output on ddo0 000 b : 0db 001 b : 1.1db (default) 010 b : 2.4db 011 b : 4.0db 100 b : 5.7db 101 b : 8.2db 110 b : 11.5db ddo0_deemphasis_270m 5:3 rw 0 h de-emphasis control for 0.27gb/s (sd-sdi) signals output on ddo0 000 b : 0db (default) 001 b : 1.2db 010 b : 2.5db 011 b : 4.1db 100 b : 6.0db 101 b : 8.5db 110 b : 12.0db ddo0_deemphasis_125m 2:0 rw 0 h de-emphasis control for 0.125gb/s (madi) signals output on ddo0 000 b : 0db (default) 001 b : 1.2db 010 b : 2.5db 011 b : 4.1db 100 b : 6.0db 101 b : 8.5db 110 b : 12.0db table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 51 of 64 proprietary & confidential www.semtech.com 1b h driver_control_ reg_2 rsvd 15:15 rw 0 h reserved. do not change. ddo1_deemphasis_5g94 14:12 rw 2 h de-emphasis control for 5.94gb/s (6gb/s uhd-sdi) signals output on ddo1 000 b : 0db 001 b : 0.3db 010 b : 0.6db (default) 011 b : 2.3 b 100 b : 4.0db 101 b : 6.6db 110 b : 10.0db ddo1_deemphasis_2g97 11:9 rw 1 h de-emphasis control for 2.97gb/s (3gb/s sdi) signals output on ddo1 000 b : 0db 001 b : 0.4db (default) 010 b : 1.5db 011 b : 3.2db 100 b : 4.9db 101 b : 7.6db 110 b : 11.0db ddo1_deemphasis_1g485 8:6 rw 1 h de-emphasis control for 1.485gb/s (hd-sdi) signals output on ddo1 000 b : 0db 001 b : 1.1db (default) 010 b : 2.4db 011 b : 4.0db 100 b : 5.7db 101 b : 8.2db 110 b : 11.5db ddo1_deemphasis_270m 5:3 rw 0 h de-emphasis control for 0.27gb/s (sd-sdi) signals output on ddo1 000 b : 0db (default) 001 b : 1.2db 010 b : 2.5db 011 b : 4.1db 100 b : 6.0db 101 b : 8.5db 110 b : 12.0db ddo1_deemphasis_125m 2:0 rw 0 h de-emphasis control for 0.125gb/s (madi) signals output on ddo1 000 b : 0db (default) 001 b : 1.2db 010 b : 2.5db 011 b : 4.1db 100 b : 6.0db 101 b : 8.5db 110 b : 12.0db table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 52 of 64 proprietary & confidential www.semtech.com 1c h driver_control_ reg_3 rsvd 15:12 rw 0 h reserved. do not change. ddo0_swing_1g485 11:8 rw 3 h differential swing (amplitude) control for 1.485gb/s (hd-sdi) sign als output on ddo0. for details refer to section 4.5.3 . ddo0_swing_270m 7:4 rw 3 h differential swing (amplitude) control for 0.27gb/s (sd-sdi) signals output on ddo0. for details refer to section 4.5.3 . ddo0_swing_125m 3:0 rw 3 h differential swing (amplitude) control for 0.125gb/s (madi) signals output on ddo0. for details refer to section 4.5.3 . 1d h driver_control_ reg_4 ddo0_swing_bypass 15:12 rw 3 h differential swing (amplitude) control for unlocked signals output on ddo0 (when reclocker is operating in bypass mode). for details refer to section 4.5.3 . takes precedence over rate-specific swing controls ddo0_swing_mute 11:8 rw 3 h differential static amplitude control for ddo0 when the output is muted. for details refer to section 4.5.3 . takes precedence over rate-specific swing controls and bypass swing control ddo0_swing_5g94 7:4 rw 3 h differential swing (amplitude) control for 5.94gb/s (6g uhd-sdi) signals output on ddo0. for details refer to section 4.5.3 . ddo0_swing_2g97 3:0 rw 3 h differential swing (amplitude) control for 2.97gb/s (3gb/s sdi) signals output on ddo0. for details refer to section 4.5.3 . 1e h driver_control_ reg_5 rsvd 15:12 rw 0 h reserved. do not change. ddo1_swing_1g485 11:8 rw 3 h differential swing (amplitude) control for 1.485gb/s (hd-sdi) sign als output on ddo1. for details refer to section 4.5.3 . ddo1_swing_270m 7:4 rw 3 h differential swing (amplitude) control for 0.27gb/s (sd-sdi) signals output on ddo1. for details refer to section 4.5.3 . ddo1_swing_125m 3:0 rw 3 h differential swing (amplitude) control for 0.125gb/s (madi) signals output on ddo1. for details refer to section 4.5.3 . table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 53 of 64 proprietary & confidential www.semtech.com 1f h driver_control_ reg_6 ddo1_swing_bypass 15:12 rw 3 h differential swing (amplitude) control for unlocked signals output on ddo1 (when reclocker is operating in bypass mode). for details refer to section 4.5.3 . also applies when the device is not locked. takes precedence over rate-specific swing controls ddo1_swing_mute 11:8 rw 3 h differential static amplitude control for ddo1 when the output is muted. for details refer to section 4.5.3 . takes precedence over rate-specific swing controls and bypass swing control ddo1_swing_5g94 7:4 rw 3 h differential swing (amplitude) control for 5.94gb/s (6g uhd-sdi) signals output on ddo1. for details refer to section 4.5.3 . ddo1_swing_2g97 3:0 rw 3 h differential swing (amplitude) control for 2.97gb/s (3gb/s sdi) signals output on ddo1. for details refer to section 4.5.3 . 20 h reclocker_ bypass rsvd 15:2 rw 0 h reserved. do not change. manual_bypass 1:1 rw 0 h used to manually by pass the retiming block in the reclocker. 0 b : retimer not bypassed 1 b : retimer bypassed the assertion of manual_bypass takes precedence irrespective of the setting of auto_bypass auto_bypass 0:0 rw 1 h selects between automatic and manual bypass of the retiming block when the reclocker is not locked. 0 b : auto-bypass is disabled 1 b : auto-bypass is enabled even if auto_bypass is asserted, the assertion of manual_bypass will still cause the retimer to be bypassed. 21 h pd_control rsvd 15:7 rw 1 h reserved. do not change. lock_sample 6:6 rw 0 h selects sampling method for lock detection 0 b : strict sampling 1 b : high-jitter sampling rsvd 5:1 rw 2 h reserved. do not change. polarity_invert 0:0 rw 0 h table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 54 of 64 proprietary & confidential www.semtech.com 22 h reserved rsvd 15:0 rw 4208 h reserved. do not change. 23 h reserved rsvd 15:0 rw 0 h reserved. do not change. 24 h reserved rsvd 15:0 rosw 0 h reserved. do not change. 25 h reserved rsvd 15:0 rw 0 h reserved. do not change. 26 h reserved rsvd 15:0 rw 2 h reserved. do not change. 27 h reserved rsvd 15:0 rw a8b h reserved. do not change. 28 h reserved rsvd 15:0 rw 3 h reserved. do not change. 29 h reserved rsvd 15:0 rw 3 h reserved. do not change. 2a h reserved rsvd 15:0 rw 3 h reserved. do not change. 2b h reserved rsvd 15:0 rw 2 h reserved. do not change. 2c h reserved rsvd 15:0 ro 0 h reserved. 2d h reserved rsvd 15:0 ro 0 h reserved. 2e h reserved rsvd 15:0 ro 0 h reserved. 2f h reserved rsvd 15:0 ro 0 h reserved. 30 h reserved rsvd 15:0 ro 0 h reserved. 31 h reserved rsvd 15:0 ro 0 h reserved. 32 h reserved rsvd 15:0 ro 0 h reserved. 33 h reserved rsvd 15:0 ro 0 h reserved. 34 h reserved rsvd 15:0 ro 0 h reserved. 35 h reserved rsvd 15:0 ro 0 h reserved. 36 h reserved rsvd 15:0 ro 0 h reserved. 37 h reserved rsvd 15:0 ro 0 h reserved. 38 h reserved rsvd 15:0 ro 0 h reserved. 39 h reserved rsvd 15:0 rw 2 h reserved. do not change. 3a h reserved rsvd 15:0 rosw 0 h reserved. do not change. 3b h reserved rsvd 15:0 rw 0 h reserved. do not change. 3c h reserved rsvd 15:0 rw 2 h reserved. do not change. 3d h reserved rsvd 15:0 rw a8b h reserved. do not change. table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 55 of 64 proprietary & confidential www.semtech.com 3e h reserved rsvd 15:0 rw 3 h reserved. do not change. 3f h reserved rsvd 15:0 rw 3 h reserved. do not change. 40 h reserved rsvd 15:0 rw 0 h reserved. do not change. 41 h reserved rsvd 15:0 ro 0 h reserved. do not change. 42 h reserved rsvd 15:0 ro 0 h reserved. 43 h reserved rsvd 15:0 ro 0 h reserved. 44 h reserved rsvd 15:0 ro 0 h reserved. 45 h reserved rsvd 15:0 ro 0 h reserved. 46 h reserved rsvd 15:0 ro 0 h reserved. 47 h reserved rsvd 15:0 ro 0 h reserved. 48 h reserved rsvd 15:0 ro 0 h reserved. 49 h reserved rsvd 15:0 ro 0 h reserved. 4a h reserved rsvd 15:0 ro 0 h reserved. 4b h reserved rsvd 15:0 ro 0 h reserved. table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 56 of 64 proprietary & confidential www.semtech.com 4c h pll_control rsvd 15:12 rw 0 h reserved. do not change. los_detection_method 11:10 rw 1 h determines the source of carrier_detect. 00 b : edge detection 01 b : strength detection force_pll_rate 9:7 rw 1 h force the pll to retime a specific data rate. 000 b : reserved 001 b : 0.270gb/s 010 b : 1.485gb/s 011 b : 2.97gb/s 100 b : 5.94gb/s 101 b : reserved 110 b : reserved 111 b : reserved used when force_pll_rate_enable is set to 1. force_pll_rate_enable 6:6 rw 0 h enables the forced pll rate override set using the force_pll_rate bits. rate_enable_125m 5:5 rw 0 h enables auto-detection of 0.125gb/s (madi) signals 0 b : 0.125gb/s signals will not be detected 1 b : 0.125gb/s signals will be detected rate_enable_5g94 4:4 rw 1 h enables auto-detection of 5.94gb/s (6g uhd-sdi) signals. 0 b : 5.94gb/s signals will not be detected 1 b : 5.94gb/s signals will be detected rate_enable_2g97 3:3 rw 1 h enables auto-detection of 2.97gb/s (3g sdi) signals. 0 b : 2.97gb/s signals will not be detected 1 b : 2.97gb/s signals will be detected rate_enable_1g485 2:2 rw 1 h enables auto-detection of 1.485gb/s (hd- sdi) signals. 0 b : 1.485gb/s signals will not be detected 1 b : 1.485gb/s signals will be detected rate_enable_270m 1:1 rw 1 h enables auto-detection of 0.27gb/s (sd-sdi) signals. 0 b : 0.27gb/s signals will not be detected 1 b : 0.27gb/s signals will be detected pll_soft_reset 0:0 rw 0 h synchronous soft-reset for the pll rate detection state machine. 0 b : normal operation of the pll rate detection state machine 1 b : resets the pll rate detection state machine table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 57 of 64 proprietary & confidential www.semtech.com 4d h reserved rsvd 15:0 rw 110 h reserved. do not change. 4e h reserved rsvd 15:0 rw 110 h reserved. do not change. 4f h pll_status retimer_bypass 15:15 ro indicates whether the retimer is active or bypassed. 0 b : retimer is active 1 b : retimer is bypassed lbr_hbr 14:14 ro indicates high-bit-rate versus low-bit-rate. 0 b : input data rate is 5.94gb/s, 2.97gb/s, 1.485gb/s, or bypass 1 b : input data rate is 270mb/s or 125mb/s detected_rate 13:11 ro indicates the current rate found by the pll rate detection state machine. 000 b : 0.125gb/s 001 b : 0.270gb/s 010 b : 1.485gb/s 011 b : 2.97gb/s 100 b : 5.94gb/s 101 b : reserved 110 b : reserved 111 b : reserved rsvd 10:10 ro reserved. locked 9:9 ro indicates if the cdr is locked or unlocked. 0 b : cdr is unlocked 1 b : cdr is locked los 8:8 ro indicates whether or not the cdr has lost the signal. 0 b : signal is present 1 b : loss of signal rsvd 7:0 ro reserved. table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 58 of 64 proprietary & confidential www.semtech.com 50 h sticky_status standby_sticky 11:11 rocw sticky bit indicating that the device entered standby mode at least once. 0 b : device has not entered standby mode since this bit was last cleared 1 b : devices has entered standby mode since this bit was last cleared sleep_sticky 10:10 rocw sticky bit indicating that the device entered sleep mode at least once 0 b : device has not entered sleep mode since this bit was last cleared 1 b : device has entered sleep mode since this bit was last cleared retimer_bypass_sticky 9:9 rocw sticky bit indicating that the retimer is/has been bypassed. 0 b : retimer has not been bypassed since this bit was last cleared 1 b : retimer has been bypassed since this bit was last cleared this bit is cleared by writing any value to it. lbr_hbr_sticky 8:8 rocw sticky bit indicating that the rate is/has been 270mb/s (low bit-rate). 0 b : rate has not been 270mb/s since this bit was last cleared 1 b : rate has been 270mb/s since this bit was last cleared this bit is cleared by writing any value to it. rate_change_sticky 7:7 rocw sticky bit indicating that a rate change has occurred. 0 b : rate has not changed since this bit was last cleared 1 b : rate has changed since this bit was last cleared this bit is cleared by writing any value to it. lock_lost_sticky 6:6 rocw sticky bit indicating that lock was lost. 0 b : lock has not been lost since this bit was last cleared 1 b : lock has been lost since this bit was last cleared this bit is cleared by writing any value to it. rsvd 5:5 rocw reserved. los_sticky 4:4 rocw sticky bit indicating a loss of signal. 0 b : signal has not been lost since this bit was last cleared 1 b : signal has been lost since this bit was last cleared this bit is cleared by writing any value to it. rsvd 3:0 rocw reserved. table 5-1: register descriptions - standard address space (continued) address register name parameter name bit slice r/w reset value description
GS6150 final data sheet rev.2 pds-060127 march 2015 59 of 64 proprietary & confidential www.semtech.com rw = read/write ro = read only rocw = read only/ clear on write rosw = read only/ set on write table 5-2: register descriptio ns - extended address space address register name parameter name bit slice r/w reset value (dec) description e4 h pll_lbw_ control_ reg_0 rsvd 15:5 rw 4 h reserved. do not change. pll_loop_bandwidth 4:0 rw 4 h sets the rate specific pll loop-bandwidth when the device is locked. 00001 b : nominal / 4 00010 b : nominal / 2 00100 b : nominal (default) 01000 b : nominal x 2 11100 b : nominal x 4 see table 2-3: ac electrical characteristics for the pll loop-bandwidth value set at each rate by each of these settings.
GS6150 final data sheet rev.2 pds-060127 march 2015 60 of 64 proprietary & confidential www.semtech.com 6. typical application circuit figure 6-1: GS6150 typical application circuit if ac coupling is required on the high-speed serial inputs and outputs by the application, a ceramic capacitor 4.7f or higher with a stable dielectric is recommended *values for c1 and c2 are chosen based on the required loading for the selected crystal xtal is optional vcc_ddo0 and vcc_ddo1 are in the range +1.2v to +2.5v notes: vcc is 1.8v *c1 *c2 1f 10f vcc_ddo1 10nf 10nf GS6150 1mw vcc_ddo0 27mhz 10nf 10f 10nf 10nf 10nf vcc 10nf 10nf in in center pad vee_core vcc_core vco_filt vee_core vcc_core rsv_39 rsv_38 vee_ddo vee_ddo vee_ddo vcc_ddo1 vss_dig vdd_dig gnd gnd gnd lf- lf+ rsv_40 rsv_41 rsv_37 vcc_ddo0 ddo0p ddo0n ddo1p ddo1n rst gpio3 gpio2 cs sclk sdout sdin xtal_buff_out xtal_out xtal/clk_in ddi_sel1 ddi_sel0/strobe gpio1 gpio0 ddi3n ddi3p ddi2n ddi2p ddi1n ddi1p ddi0n ddi0p out in in out 1 in in in in in in in in out out io io io io in in out c lf
GS6150 final data sheet rev.2 pds-060127 march 2015 61 of 64 proprietary & confidential www.semtech.com 7. package and ordering information 7.1 package dimensions figure 7-1: package dimensions 6.00 a b 6.00 2x c 0.10 2x c 0.10 48x seating plane c 0.08 c 0.10 0.900.10 0.02 +0.03 ?0.02 0.20 ref c datum b datum a 4.650.15 c 0.10 a b m c 0.10 a b m detail a 4.650.15 0.200.050 c 0.05 m c 0.07 a b m 48x datum a or b 0.40/2 0.40 0.400.10 detail a (scale 3:1) notes: 1. dimensions and tolerance is in conformance to asme y14.5?1994 2. all dimensions are in millimeters or in degrees
GS6150 final data sheet rev.2 pds-060127 march 2015 62 of 64 proprietary & confidential www.semtech.com 7.2 recommended pcb footprint figure 7-2: GS6150 pcb footprint 7.3 packaging data center pad 4.3 4.3 5.8 5.8 0.2 0.6 0.4 note: all dimensions in millimeters table 7-1: packaging data parameter value package type 6mm x 6mm 48-pin qfn moisture sensitivity level ( note 1 )3 junction to case thermal resistance, j-c 26.2c/w junction to air thermal resistance, j-a 21.6c/w junction to board thermal resistance, j-b 4.4c/w psi, 0.2c/w pb-free and rohs compliant yes note: 1. value per jedec j-std-020c
GS6150 final data sheet rev.2 pds-060127 march 2015 63 of 64 proprietary & confidential www.semtech.com 7.4 marking diagram figure 7-3: GS6150 marking diagram 7.5 solder reflow profile figure 7-4: maximum pb-free solder reflow profile 7.6 ordering information GS6150 xxxxe3 yyww pin 1 id xxxx - last 4 digits of assembly lot e3 - pb-free & green indicator yyww - date code 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3c/sec max 6c/sec max table 7-2: ordering information part number package temperature range GS6150-ine3 pb-free 48-pin qfn -40c to 85c GS6150-inte3 pb-free 48-pin qfn (250pc. tape and reel) -40c to 85c GS6150-inte3z pb-free 48-pin qfn (2.5k tape and reel) -40c to 85c
? semtech 2014 all rights reserved. reproduction in whole or in part is prohib ited without the prior written consent of the copyright owner. t he information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any licens e under patent or other industrial or intellectual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum rati ngs or operation outside the specified range. semtech products are not designed, intended, authoriz ed or warranted to be suitable for use in life- support applications, devices or systems or other crit ical applications. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized ap plication, the customer shall indemnify and hold semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fee s which could arise. notice: all referenced brands, product names, service names and trademarks are the property of their respective owners . document identification final data sheet the product is in production. semtech reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GS6150 final data sheet rev.2 pds-060127 march 2015 64 of 64 64 proprietary & confidential contact information semtech corporation 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111, fax: (805) 498-3804 www.semtech.com caution electrostatic sensitive devices do not open packages or handle except at a static- free workstation

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